Sampling circuit, phase reference detecting circuit and sampling clock shifting circuit

ABSTRACT

A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (φ2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (φ2) so that the sampling clock (φ2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (φ2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a sampling circuit, a phase referencedetecting circuit and a sampling clock shifting circuit. A phasereference detecting circuit and a sampling clock shifting circuit areused in a sampling circuit. A sampling circuit is used to reproduce anddigitalize a color image signal, for example.

2. Description of the Background Art

FIG. 26 is a circuitry diagram showing a structure of a conventionalsampling circuit. Resistors 20a, 20b and 20c are connected to an NPNtransistor 21a. The operating bias of the NPN transistor 21a isdetermined by these resistors and power sources V_(CC) and V_(EE). AnNPN transistor 21b is also connected to the NPN transistor 21a through acapacitor 19b and a pre-set resistor 22.

A sampling clock received at an input terminal IN is a sinusoidal wave.The capacitor 19a allows only an ac component to be transmitted to abase of the transistor 21a which is biased to a voltage whichcorresponds to a voltage ratio of the resistors 20a and 20b. From anemitter and a collector of the transistor 21a, two different signalswhich are shifted by 180° from each other are outputted. One of thesesignals is supplied to the capacitor 19b and the other is supplied tothe pre-set resistor 22. These signals are then synthesized and suppliedto a base of the transistor 21b. A synthesized signal has a phase lagwhich corresponds to a time constant which is defined as a product of acapacitance value of the capacitor 19b and a resistance of the pre-setresistor 22. The transistor 21b and a resistor 20d form an emitterfollower circuit which converts an impedance of the synthesized signal.A resultant signal is outputted at an output terminal OUT.

In short, a phase difference of the sampling clock against asignal-to-be-sampled is adjusted by means of the time constant of theresonance circuit which is formed by the capacitor 19b and the pre-setresistor 22. As a result of adjustment of the phase difference of thesampling clock, sampling points are adjusted.

Having such a structure as above, the conventional sampling circuit issusceptible to an influence of the structural components such as theresistors, the capacitor and the transistors, as well as anenvironmental temperature, a fluctuation in a power source voltage andother factors. To a further disadvantage, it is impossible to automatizeadjustment since feedback control is impossible.

SUMMARY OF THE INVENTION

A first aspect of the present invention is related to a sampling circuitfor sampling an analog signal-to-be-sampled using a sampling clock, thesignal-to-be-sampled including a primary signal which is obtained bydemodulating a carrier and a fore signal which has the same frequency asthe carrier and which is precedent to the primary signal, the samplingclock having a frequency which is m times as high as the frequency ofthe carrier (m is an integer). The sampling circuit comprises: (a) anA/D converter for sampling the signal-to-be-sampled in accordance withthe sampling clock and generating a digital basic signal; (b) a phasereference detecting circuit for generating at least three delayed basicsignals having different phases from each other and being obtained bydelaying the basic signal in synchronism with the sampling clock, and aphase difference signal which indicates a reference of a phase of saidsampling clock; (c) a phase difference detecting circuit for generatinga phase difference signal from the delayed basic signals, the phasedifference signal indicating a phase difference between the fore signaland the basic signal when the phase reference signal is active; and (d)a sampling clock shifting circuit for shifting the phase of the samplingclock in accordance with the phase difference signal only when the phasereference signal is active, to thereby supply the sampling clock to theA/D converter and the phase reference detecting circuit.

According to a second aspect of the present invention, in the samplingcircuit of the first aspect, the phase reference signal is activatedduring one cycle of the sampling clock which starts from a time ofactivation of the sampling clock within a range of 1/2m cycle from a midvalue of the fore: signal toward both a prior time and a future time.

According to a third aspect of the present invention, in the samplingcircuit of the second aspect, the integer m is 4, and the phasereference detecting circuit includes: (b-1) first signal transmittingmeans having an input terminal for receiving the basic signal and anoutput terminal for transmitting a signal which is received at the inputterminal in response to activation of the sampling clock as a firstdelayed basic signal of the delayed basic signals; (b-2) second signaltransmitting means having an input terminal for receiving the firstdelayed basic signal and output terminal for transmitting a signal whichis supplied to the input terminal of the second signal transmittingmeans in response to activation of the sampling clock as a seconddelayed basic signal of the delayed basic signals; (b-3) third signaltransmitting means having an input terminal for receiving the seconddelayed basic signal and an output terminal for transmitting a signalwhich is supplied to the input terminal of the third signal transmittingmeans in response to activation of the sampling clock as a third delayedbasic signal of the delayed basic signals; (b-4) fourth signaltransmitting means having an input terminal for receiving the thirddelayed basic signal and an output terminal for transmitting a signalwhich is supplied to the input terminal of the fourth signaltransmitting means in response to activation of the sampling clock as afourth delayed basic signal of the delayed basic signals; and (b-5) acomparator for outputting the phase reference signal which is activatedwhen the first delayed basic signal is smaller than the fourth delayedbasic signal and is equal to or smaller than the second delayed basicsignal during the specified one cycle of the fore signal.

Alternatively, in the third aspect of the present invention, the integerm is 4, and the phase reference detecting circuit includes: (b-1) firstsignal transmitting means having an input terminal for receiving thebasic signal and an output terminal for transmitting a signal which isreceived at the input terminal in response to activation of the samplingclock as a first delayed basic signal of the delayed basic signals;(b-2) second signal transmitting means having an input terminal forreceiving the first delayed basic signal and an output terminal fortransmitting a signal which is supplied to the input terminal of thesecond signal transmitting means in response to activation of thesampling clock as a second delayed basic signal of the delayed basicsignals; (b-3) third signal transmitting means having an input terminalfor receiving the second delayed basic signal and an output terminal fortransmitting a signal which is supplied to the input terminal of thethird signal transmitting means in response to activation of thesampling clock as a third delayed basic signal of the delayed basicsignals; (b-4) fourth signal transmitting means having an input terminalfor receiving the third delayed basic signal and an output terminal fortransmitting a signal which is supplied to the input terminal of thefourth signal transmitting means in response to activation of thesampling clock as a fourth delayed basic signal of the delayed basicsignals; and (b-5) a comparator for outputting the phase referencesignal which is activated when the fourth delayed basic signal is largerthan the first delayed basic signal and is equal to or smaller than thethird delayed basic signal during the specified one cycle of the foresignal.

Alternatively, the integer m is 4, and the phase reference detectingcircuit includes: (b-1) first signal transmitting means having an inputterminal for receiving the basic signal and an output terminal fortransmitting a signal which is received at the input terminal inresponse to activation of the sampling clock as a first delayed basicsignal of the delayed basic signals; (b-2) second signal transmittingmeans having an input terminal for receiving the first delayed basicsignal and an output terminal for transmitting a signal which issupplied to the input terminal of the second signal transmitting meansin response to activation of the sampling clock as a second delayedbasic signal of the delayed basic signals; (b-3) third signaltransmitting means having an input terminal for receiving the seconddelayed basic signal and an output terminal for transmitting a signalwhich is supplied to the input terminal of the third signal transmittingmeans in response to activation of the sampling clock as a third delayedbasic signal of the delayed basic signals; and (b-4) a first comparatorfor outputting the phase reference signal which is activated when thesecond delayed basic signal is larger than the first delayed basicsignal and the third delayed basic signal is equal to or smaller thanthe second delayed basic signal during the specified one cycle of thefore signal.

According to a fourth aspect of the present invention, in the samplingcircuit of the third aspect, the phase difference detecting circuitincludes (c-1) a second comparator for comparing the third and the firstdelayed basic signals and for outputting an equivalent signal which isactivated when the third and the first delayed basic signals are equalto each other and a non-equivalent signal which is activated when thethird delayed basic signal is larger than the first delayed basicsignal, and the equivalent signal and the non-equivalent signal form thephase difference signal.

According to a fifth aspect of the present invention, in the samplingcircuit of the third aspect, the phase difference detecting circuitincludes: (c-1) a second comparator for outputting an equivalent signalwhich is activated when the third and the second delayed basic signalsare equal to each other; and (c-2) a third comparator for outputting anon-equivalent signal which is activated when the third delayed basicsignal is equal to or larger than the first delayed basic signal, andthe equivalent signal and the non-equivalent signal form the phasedifference signal.

According to a sixth aspect of the present invention, in the samplingcircuit of the second aspect, the phase difference signal is formed byan equivalent signal which is activated when the signal-to-be-sampled issampled at an optimal timing and a non-equivalent signal whichindicates, during activation of the phase reference signal, that theactivation expresses a timing delay of sampling. The sampling clockshifting circuit includes: (d-1) delaying means for receiving a shiftingcontrol signal and the sampling clock and delaying the sampling clock inaccordance with the shifting control signal; (d-2) a counter forcounting the sampling clock which is delayed by the delaying means andgenerating the shifting control signal, a direction in which the countercounts being determined by the non-equivalent signal; and (d-3) counteroperation allowing means for allowing the counter to count only when thenon-equivalent signal is not active but the phase reference signal isactive.

In the sixth aspect of the present invention, the delaying means mayinclude: (d-1-1) a plurality of delaying elements which are, seriallyconnected to each other; (d-1-2) the same number of input terminals asthe plurality of the delaying elements, each receiving an output of anassociated one of the delaying elements; and (d-1-3) a selector forselectively outputting one of data supplied to the input terminals inaccordance with the shifting control signal.

In the sixth aspect of the present invention, the counter may include(d-2-1) an enable terminal for controlling an operation of the counter,and the counter operation allowing means may include: (d-3-1) aninverter for reversing the equivalent signal; and (d-3-2) a logicelement having an input terminal for receiving an output of the inverterand the phase reference signal and an output terminal for outputting alogical product which is obtained at the input terminal of the logicelement, the output terminal of the logic element being connected to theenable terminal.

According to a seventh aspect of the present invention, in the samplingcircuit of the sixth aspect, the sampling clock shifting circuit furtherincludes (d-4) counting direction reversing means for reversing acounting direction when the counter registers a maximum count or aminimum count.

In the seventh aspect of the present invention, the counter outputs acarry-out signal which is activated when the counter registers themaximum count or the minimum count, and the counting direction reversingmeans includes: (d-4-1) a flip-flop for outputting a reversing controlsignal which is set by the carry-out signal and reset by the equivalentsignal; and (d-4-2) a logic element for transmitting the non-equivalentsignal in response to deactivation of the reversing control signal andfor reversing and transmitting the non-equivalent signal in response toactivation of the reversing control signal.

According to an eighth aspect of the present invention, in the samplingcircuit of the seventh aspect, the delaying means shifts the samplingclock within a range of 3/8 cycle of the fore signal.

According to a ninth aspect of the present invention, in the samplingcircuit of the seventh aspect, the sampling clock shifting circuitfurther includes (d-5) counting stopping means for prohibiting countingup when the counter registers the maximum count and prohibiting countingdown when the counter registers the minimum count.

A tenth aspect of the present invention is related to a phase referencedetecting circuit for finding a basic signal which is obtained bysampling a signal-to-be-sampled in accordance with a sampling clockwhich is activated at intervals of 1/4 cycle of the signal-to-be-sampledand for outputting a phase reference signal which serves as a referenceto determine whether the signal-to-be-sampled is sampled with apredetermined phase and which is activated in response to the basicsignal, the phase reference detecting circuit comprising: (a) firstsignal transmitting means having an input terminal for receiving thebasic signal and an output terminal for transmitting a signal which isreceived at the input terminal in response to activation of the samplingclock, the signal from the output terminal being outputted as a firstdelayed basic signal of the delayed basic signals; (b) second signaltransmitting means having an input terminal for receiving the firstdelayed basic signal and an output terminal for transmitting a signalwhich is supplied to the input terminal of the second signaltransmitting means in response to activation of the sampling clock, thesignal from the output terminal being outputted as a second delayedbasic signal of the delayed basic signals; (c) third signal transmittingmeans having an input terminal for receiving the second delayed basicsignal and an output terminal for transmitting a signal which issupplied to the input terminal of the third signal transmitting means inresponse to activation of the sampling clock, the signal from the outputterminal being outputted as a third delayed basic signal of the delayedbasic signals; and (d) a first comparator for outputting the phasereference signal which is activated when the second delayed basic signalis larger than the first delayed basic signal and the third delayedbasic signal is equal to or smaller than the second delayed basic signalduring the specified one cycle of the fore signal.

An eleventh aspect of the present invention is related to a samplingclock shifting circuit for shifting a phase of a sampling clock duringsampling of a signal-to-be-sampled in accordance with the sampling clockwhich is activated at intervals of 1/4 cycle of the signal-to-be-sampledin such a manner that the signal-to-be-sampled is sampled with apredetermined phase, the sampling clock shifting circuit receiving:(x-1) a coincidence signal which indicates whether a phase of thesampling clock is deviated from the predetermined phase; (x-2) a phasereference signal which expresses a deviation between the phase of thesampling clock and the predetermined phase; and (x-3) a non-coincidencesignal which expresses a direction of the deviation between the phase ofthe sampling clock and the predetermined phase when the phase referencesignal is active. The sampling clock shifting circuit comprises: (a)delaying means for receiving a shifting control signal and the samplingclock and &laying the sampling clock in accordance with the shiftingcontrol signal; (b) a counter for counting the sampling clock which isdelayed by the delaying means and generating the shifting controlsignal, a direction in which the counter counts being determined by thenon-coincidence signal; and (c) counter operation allowing means forallowing the counter to count only when the coincident signal is notactive but the phase reference signal is active.

In the sampling circuit of the first aspect, when the phase of thesampling clock does not have a proper phase difference with respect tothe phase of the signal-to-be-sampled, the sampling clock shiftingcircuit shifts the phase of the sampling clock. Whether the phasedifference has a proper amount is detected by the phase differencedetecting circuit in accordance with the basic signal which is obtainedby digitalizing the signal-to-be-sampled using the sampling clock.Hence, the phase of the sampling clock is adjusted utilizing a feedbackregarding the same.

Only when combined with the phase reference which is provided by thephase reference detecting circuit, the phase difference signal outputtedby the phase difference detecting circuit serves as valid informationuseful for shifting the phase of the sampling clock. For this reason,the sampling clock shifting circuit shifts the phase of the samplingclock in accordance with the phase difference signal only when the phasereference signal is active. Such correction of the phase of the samplingclock is performed during a specified one cycle of the fore signal.

In the sampling circuit of the second aspect, the phase reference signalis activated within a predetermined cycle of the fore signal. Since thepredetermined cycle is 1/m cycle, the sampling clock is always activewithin this cycle, and therefore, there is always the basic signal whichis obtained by sampling the fore signal.

In the sampling circuit of the third aspect, the signal-to-be-sampled issampled at the sampling clock which has a frequency four times as highas that of the signal-to-be-sampled. Hence, it is possible to obtain thedelayed basic signals, which are compared with each other, from therespective output terminals of the first to the third signaltransmitting means which are serially connected in this order.

In the sampling circuit of the fourth aspect, the equivalent signal isactivated, regarding sampling at a time when the fore signal records itsmid value as an optimal sampling timing. During activation of the phasereference signal, when the third delayed basic signal is larger than thefirst delayed basic signal, the non-equivalent signal indicates thatsampling timing is lagged behind the optimum sampling timing.

In the sampling circuit of the fifth aspect, the equivalent signal isactivated, regarding sampling at a time which is deviated by 1/8 cycleof the fore signal from the time of the mid value of the fore signal asan optimal sampling timing. During activation of the phase referencesignal, when the third delayed basic signal is equal to or smaller thanthe first delayed basic signal, the non-equivalent signal indicates thatsampling timing is lagged behind the optimum sampling timing.

In the sampling circuit of the sixth aspect, since the counter operatesunder the control of the counter operation allowing means, by means ofthe non-equivalent signal, it is possible to change the countingdirection of the counter in accordance with an advance or a delay ofsampling timing in such a manner that the sampling timing becomesoptimum. A result of the counting of the counter controls a delay of thesampling clock as the shifting control signal.

In the sampling circuit of the seventh aspect, in a case where thenon-equivalent signal stays at the same value, when the counterregisters a maximum count or a minimum count, it is judged that no moreshifting of the sampling clock in the current counting direction willnot optimize the sampling timing. Following this, the sampling clock isshifted in the reverse direction to optimize the sampling timing.Sampling is always performed during a period from 1/8 cycle of the foresignal leading the optimal sampling timing until 1/8 cycle of the foresignal after the optimal sampling timing. Hence, where the samplingtiming leads the optimal sampling timing, by delaying the sampling clockby at most 1/4 cycle of the fore signal, the basic signal is obtained asit should be by sampling which is timed at the optimal sampling timing.To the contrary, where the sampling timing is lagged behind the optimalsampling timing, the sampling clock is advanced by at most 1/4 cycle ofthe fore signal.

In the sampling circuit of the eighth aspect, it is possible to shift by1/4 cycle of the fore signal for sampling which is timed any timing andfor shifting of the sampling clock in any direction.

In the sampling circuit of the ninth aspect, the counting direction ofthe counter is switched by the counting direction reversing means whenthe counter registers a maximum count. Hence, the counter does notperform counting even if the sampling clock shifting circuit isinstructed to initiate counting.

In the phase reference detecting circuit of the tenth aspect, since theserially sampled basic signals are compared with each other, it ispossible to obtain the first to the third delayed basic signals from therespective output terminals of the first to the third signaltransmitting means.

In the sampling clock shifting circuit of the eleventh aspect, since thecounter operates under the control of the counter operation allowingmeans, by means of the non-coincident signal, it is possible to changethe counting direction of the counter in accordance with an advance or adelay of sampling timing in such a manner that the sampling timingbecomes optimum. Since it is only when the phase reference signal isactive that the non-coincident signal correctly expresses the directionof a deviation of the phase of the sampling clock with respect to thepredetermined phase, the operation of the counter of when the phasereference signal is inactive is stopped by the counter operationallowing means.

As heretofore described, according to the present invention, by means offeedback control of the sampling circuit utilizing a digital circuit,various effects are created such as a reduction in the number ofdiscrete components, automatized adjustment and various modes ofcontrol.

In the sampling circuit of the first aspect, the phase of the samplingclock is adjusted utilizing a feedback regarding the same. Further,since the phase of the sampling clock is corrected within the specifiedone cycle of the fore signal, it is possible to automatically adjust thephase of the sampling clock such that a phase difference of the samplingclock with respect to the primary signal which is supplied later has aproper amount.

In the sampling circuit of the second aspect, it is possible to generatethe phase reference signal in an easy manner only by comparing thevalues of the delayed basic signals.

In the sampling circuit of the third aspect, it is possible to generatethe phase reference signal with a simple structure.

In the sampling circuit of the fourth aspect, it is possible to detectwhether the sampling timing is optimal by means of the equivalentsignal. Particularly during activation of the phase reference signal,whether the sampling timing is later is judged by means of thenon-equivalent signal.

Since sampling at a time when the fore signal records its mid value isjudged as an optimal sampling timing, the fourth aspect of the presentinvention is suitable especially to sampling of a color signal of theNTSC method.

In the sampling circuit of the fifth aspect, it is possible to detectwhether the sampling timing is optimal by means of the equivalentsignal. Particularly during activation of the phase reference signal,whether the sampling timing is later is judged by means of thenon-equivalent signal.

Since sampling at a time which is deviated by 1/8 cycle of the foresignal from the time of the mid value of the fore signal is judged as anoptimal sampling timing, the fifth aspect of the present invention issuitable especially to sampling of a color signal of the PAL method.

In the sampling circuit of the sixth aspect, it is possible to optimizethe sampling timing by delaying the sampling clock.

In the sampling circuit of the seventh aspect, the sampling clock may beshifted only by at least 1/4 cycle of the fore signal regardless ofwhether the sampling timing leads or lags behind the optimal samplingtiming.

In the sampling circuit of the eighth aspect, it is possible to reducethe shifting amount of the sampling clock to optimize the samplingtiming, and therefore, it is possible to adjust the sampling clock sothat sampling is smoothly and optimally performed.

In the sampling circuit of the ninth aspect, the sampling clock shiftingcircuit receives an instruction for counting up from outside immediatelybefore the counter registers a maximum count. Since an instruction forcounting down is supplied after this, it is judged that the optimalsampling timing approximately coincides with the activation of thesampling clock. Hence, there is no need to further shift the samplingclock. In other words, unnecessary malfunction due to the countingdirection reversing means is avoided.

In the phase reference detecting circuit of the tenth aspect, it ispossible to generate the phase reference signal with a simple structure.

In the sampling clock shifting circuit of the eleventh aspect, it ispossible to optimize the sampling timing by delaying the sampling clock.

Accordingly, it is an object of the present invention to obtain asampling circuit in which a sampling clock is automatically activated atan optimal timing by means of feedback control and hence which is notsusceptible to an influence of structural components, an environmentaltemperature, a fluctuation in a power source voltage and other factors.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a waveform diagram schematically showing a construction of acolor image signal to which the present invention is applicable;

FIG. 2 is a circuitry diagram showing a structure of a sampling circuitaccording to a first preferred embodiment of the present invention;

FIG. 3 is a waveform diagram of a waveform of a burst gate pulse;

FIG. 4 is a circuitry diagram showing an example of a structure of aphase reference detecting circuit;

FIGS. 5 to 8 are waveform diagrams of a burst signal;

FIG. 9 is a timing chart illustrating generation of a phase referencesignal;

FIG. 10 is a vector diagram showing a phase of a burst signal in theNTSC method;

FIG. 11 is a circuitry diagram showing an example of a structure of aphase difference detecting circuit;

FIG. 12 is a circuitry diagram showing an example of a structure of asampling clock shifting circuit;

FIGS. 13 to 15 are timing charts showing waveforms of signals in thefirst preferred embodiment;

FIG. 16 is a timing chart showing waveforms of an original clock andoutputs of delaying elements;

FIG. 17 is a graph schematically illustrating shifting of a samplingclock;

FIG. 18 is a circuitry diagram showing a structure of a sampling circuitaccording to a third preferred embodiment of the present invention;

FIG. 19 is a circuitry diagram showing an example of a structure of aphase reference detecting circuit;

FIG. 20 is a circuitry diagram showing other example of a structure ofthe phase reference detecting circuit;

FIG. 21 is a timing chart showing a relation between a phase referencesignal, a basic signal and delayed basic signals;

FIG. 22 is a circuitry diagram showing still other example of astructure of the phase reference detecting circuit;

FIG. 23 is a circuitry diagram showing a further example of a structureof the phase reference detecting circuit;

FIG. 24 is a circuitry diagram showing a structure of a phase differencedetecting circuit according to a fourth preferred embodiment of thepresent invention;

FIG. 25 is a vector diagram showing a phase of a burst signal in the PALmethod; and

FIG. 26 is a circuitry diagram showing a structure of a conventionalsampling circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A. Background Technique

For a better understanding of the present invention, a method ofreproducing a color image signal to which the present invention isapplied will be described before describing preferred embodiments of thepresent invention.

FIG. 1 is a waveform diagram schematically showing a construction of acolor image signal. The color image signal is obtained by synthesizing asynchronization signal, a color signal and a luminance signal. Receivinga color image signal, a receiver unit separates the color image signalinto a synchronization signal, a color signal and a luminance signal,and processes these signals by demodulation or other treatments.

The present invention is related in particular to a technique ofprocessing a color image signal. A color image signal E, which isobtained by modulating a chrominance subcarrier f_(sc) by twocolor-difference signals I and Q by quadrature two phase modulation, ismodulated with a luminance signal Y in a frequency multiplexing manneras can be seen in Eq. 1. For instance, the chrominance subcarrier f_(sc)is set at 455/2·f_(H) =3.579545 MHz while the color-difference signals Iand Q are set to have a bandwidth of 1.5 MHz and a bandwidth of 0.5 MHz,respectively. ##EQU1## where the symbol B-Y represents acolor-difference signal for blue and the symbol R-Y represents acolor-difference signal for red.

When a color signal included in the color image signal E in which aplurality of signals are multiplexing-modulated is to be directlydigitalized (i.e., before demodulating), to make it easy to separate thecolor image signal E into the two color-difference signals I and Q bydemodulating the color image signal E with respect to the twocolor-difference signals I and Q, in most cases, the chrominancesubcarrier f_(sc) multiplied by an integer, i.e., f_(samp) =m f_(sc) (m:integer) is selected as a sampling frequency f_(samp) of a samplingclock which is used for digitalization. To satisfy the sampling theorem,m>2 should hold. However, in general, the chrominance subcarrier f_(sc)is set with m=4 satisfied for ease of separation and synthesizing, forease of processing between scanning lines and between flames, and forease of physical design of a pre-filter and a post-filter.

Phases of the color-difference signals I and Q with respect tochrominance subcarrier determine a color phase. Hence, in digitalizing acolor signal, it is necessary to optimize not only the samplingfrequency but also the phase of a sampling clock.

The reason can be readily understood by considering a case where a colorsignal is digitalized with the phase of a sampling clock deviated froman optimum phase. When data obtained by digitalization is demodulatedand separated into two color-difference signals, each color-differencesignal includes a component of the other color-difference signal whichmanifests itself as a distorted color phase. Such residual componentsare created due to a deviation of the sampling phase. Hence, to preventdistortion in a color phase, the phase of the sampling clock withrespect to the sampling clock must be optimized.

The present invention utilizes a fact that besides the component whichis expressed by Eq. 1, the color signal includes a color burst signalwhich is a fore signal which appears prior to the component which isexpressed by Eq. 1 as shown in FIG. 1. In other words, the point of thepresent invention is to optimize the phase of the sampling clock withrespect to the color burst signal and to thereafter digitalize a primaryportion of the color signal which appears after the color burst signalby using such an optimized sampling clock.

B. First Preferred Embodiment (b-1) Outline of Structure and Operation

FIG. 2 is a circuitry diagram showing a structure of a sampling circuit100 according to a first preferred embodiment of the present invention.The sampling circuit 100 comprises an A/D converter 1, a phase referencedetecting circuit 4, a phase difference detecting circuit 5 and asampling clock shifting circuit 2.

The A/D converter 1 performs sampling at a timing when a sampling clockφ₂ is activated so that a color signal supplied to the A/D converter 1is A/D converted into a basic signal D_(<n:0>). The sampling clock φ₂used here is shifted by the sampling clock shifting circuit 2 so as tobe activated at an optimum time during the sampling.

To shift the sampling clock shifting circuit 2 in such a manner, it isnecessary to detect a deviation of the phase of the sampling clock φ₂from the optimum timing. To this end, the phase difference detectingcircuit 5 supplies an equivalent signal EQU and a non-equivalent signalUPDN which form a phase difference signal to the sampling clock shiftingcircuit 2 so that the sampling clock shifting circuit 2 is provided withinformation regarding the deviation of the phase. It is to be noted,however, that the equivalent signal EQU and the non-equivalent signalUPDN do not always have valid information.

To detect a phase difference between the color signal and the samplingclock φ₂, it is necessary to define a base time of the sampling clockφ₂. Since the sampling clock φ₂ is activated cyclically again and again,the sampling clock φ₂ may lead the color signal at some point but may belagged behind at some other point. For this reason, the phase differencecannot be known unless the base time is determined.

To determine the base time, the phase reference detecting circuit 4generates a phase reference signal ORG and supplies the same to thesampling clock shifting circuit 2. Since the phase reference signal ORGis referred to, the information regarding the phase difference containedin the equivalent signal EQU and the non-equivalent signal UPDN becomesvalid.

The phase reference detecting circuit 4 delays the basic signalD_(<a:0>) into at least three delayed basic signals which have differentphases from each other. From these delayed basic signals, the phasereference detecting circuit 4 generates the phase reference signal ORGin accordance with a predetermined rule.

Thus, since a feedback regarding the phase; of the sampling clock φ₂ isutilized, it is possible to automatically sample the color signal at anoptimum timing.

(b-2) Details of Structural Components Regarding Structure and Operation

The color signal of the image signal is supplied to an input terminalCIN which is connected to an analog input terminal AIN of the A/Dconverter 1. The A/D converter 1 samples an analog signal which isreceived at the analog input terminal AIN at a timing of the samplingclock φ₂ which is supplied to a clock terminal CLK. As a result of thesampling, the digital (n+1)-bit basic signal D_(<n:0>) is obtained fromthe color signal. The basic signal D_(<n:0>) is outputted at an(n+1)-bit output terminal DO_(<n:0>).

The phase reference detecting circuit 4 receives a burst gate pulse BGPwhich will be described later through an input terminal BIN and thebasic signal D_(<n:0>) through an (n+1)-bit input terminal DI_(<n:0>).The sampling clock φ₂ is supplied to the clock terminal CLK. The basicsignal D_(<n:0>) is delayed at timing when the sampling clock φ₂ isactivated, whereby three delayed basic signals DA_(<n:0>), DB_(<n:0>)and DC_(<n:0>) are generated which are, outputted respectively at outputterminals DOA_(<n:0>), DOB_(<n:0>) and DOC_(<n:0>). The reason forgenerating the three delayed basic signals DA_(<n:0>), DB_(<n:0>) andDC_(<n:0>) is to make it possible to compare the values of seriallysampled basic signals with each other at the same time. The phasereference signal ORG is outputted at an output terminal L₀.

FIG. 3 is a waveform diagram of a waveform of the burst gate pulse BGP.The burst gate pulse BGP is a pulse signal which is activated tocoincide with one cycle of an intermediate portion of the color burstsignal of the color signal during a vertical retrace line interval. Inthe present invention, a primary portion of the color signal isoptimally sampled by optimally adjusting the phase of the sampling clockto the burst signal. Such sampling is possible because the primaryportion of the color signal is modulated by a carrier which is the sameas the burst signal.

In other words, the phase difference of the sampling clock with respectto the burst signal is detected during the vertical retrace lineinterval. A premise is that the burst gate pulse BGP rises to "H" levelwhen activated.

FIG. 4 is a circuitry diagram showing an example of a structure of thephase reference detecting circuit 4. The phase reference detectingcircuit 4 comprises (n+1)-bit D-type flip-flops 6b, 6c and 6d which areserially connected to each other, (n+1)-bit magnitude comparators 7a and7b, an OR gate 8 and an AND gate 9. The D-type flip-flops 6b, 6c and 6deach include a D-input terminal, a Q-output terminal and a T-inputterminal. When a signal supplied to the T-input terminal is activated,each D-type flip-flop transmits data which is supplied to the D-inputterminal to the Q-output terminal. The D-input terminal of the D-typeflip-flop 6b is connected to the input terminal DI_(>n:0>) so as toreceive the basic signal D_(<n:0>). On the other hand, the T-inputterminals of all of the D-type flip-flops 6b, 6c and 6d are connected tothe clock terminal CLK so as to receive the sampling clock φ₂. Hence,respectively from the Q-input terminals of the D-type flip-flops 6b, 6cand 6d, a first delayed basic signal DC_(<n:0>), a second delayed basicsignal DB_(<n:0>) and a third delayed basic signal DA_(<n:0>) which haveprogressively shorter delay times are outputted. Although equally beinga basic signal, these three delayed basic signals are sampled atdifferent sampling timing. The phase reference signal ORG is obtained bycomparing the values of these delayed basic signals in accordance with apredetermined rule which will be described below.

A case where the frequency of the sampling clock φ₂ is four times higherthan the frequency of a carrier of a color signal will be described asan example as in Description of the Background Art. In this case, evenif a quarter of the cycle of the burst signal is set at an optionaltime, there is always a sampling time during that quarter cycle.However, to detect a phase difference by comparing the values of thesampled basic signals, the values and the phases of the basic signalsmust correspond to each other among the basic signals;. Hence, thequarter cycle to be considered to generate the phase reference signalORG can be defined around a time at which the burst signal has its midvalue.

FIGS. 5 to 8 are waveform diagrams of the burst signal for explainingthe predetermined rule to be followed in generating the phase referencesignal ORG. In FIGS. 5 to 8, denoted at reference character L is aquarter cycle which expands around the point of the mid value of theburst signal and during which the burst signal monotonously increases.Here, for convenience of description, the point of the mid value of theburst signal during the period L is θ=0° and one cycle of the burstsignal is 360°, in which case the period L is defined as a period when θ=-45° -45° holds.

FIG. 5 illustrates sampling at θ=0°, 90°, 180°, 270° , . . . while FIG.6 illustrates sampling at 0°<θ<45°, 90°<θ<135°, 180°<θ<225°, 270°<θ<315°, . . . FIG. 7 illustrates sampling at θ=45°, 135°, 225°, 315° , . . .while FIG. 8 illustrates sampling at -45°<θ<0°, 45°<θ<90°, 135°<θ<225°,315°<θ<360° , . . . Since the frequency of the sampling clock is fourtimes as high as the frequency of the burst signal, the basic signalseach have an equivalent value every four samplings.

As can be seen from FIGS. 5 to 8, a value which is used as a base of thesampling clock is to be selected during the period L, such a base may bea time when a value S_(n) of the basic signal which satisfies thefollowing conditions is sampled.

    S.sub.n ≦S.sub.n+1 and S.sub.n+1 >S.sub.n+2         (Eq. 2)

It is to be noted here that the values S_(n), S_(n+1), S_(n+2) andS_(n+3) of the basic signal are sampled at progressively slower timingin this order and therefore have phase differences of 90°.

Thus, judgement performed by the magnitude comparator 7a and the OR gate8 is in light of the first condition of Eq. 2, and judgement performedby the magnitude comparator 7b is in light of the second condition ofEq. 2. By creating a logical product of the two judgement results by theAND gate 9, a comprehensive judgement in light of Eq. 2 as a whole isyielded.

The AND gate 9 has an input terminal which is connected to the inputterminal BIN so as to receive the burst gate pulse BGP. Since a logicalproduct is found by the AND gate 9 also with respect to the burst gatepulse BGP, only one phase reference signal ORG is generated for one,burst signal.

FIG. 9 is a timing chart illustrating generation of the phase referencesignal ORG. The value of the basic signal gradually varies as Y₁, Y₂,Y₃, . . . A variation in the value of the basic signal is in accordancewith a change in the sampling clock φ₂ since the A/D converter 1performs sampling at the timing of the sampling clock φ₂. Assume herethat a set of values Y₅, Y₆ and Y₇ of the basic signal satisfies Eq. 2,Eq. 3 below is satisfied.

    Y.sub.5 ≦Y.sub.6 and Y.sub.6 >Y.sub.7               (Eq. 3)

As described earlier, the basic signal has an equivalent value everyfour samplings with respect to the burst signal. Hence, other set ofvalues Y₁, Y₂, Y₃ or Y₉, Y₁₀, Y₁₁ also satisfies Eq. 2. On the otherhand, the burst gate pulse BGP is activated only for one cycle of theburst signal, i.e., for only four cycles of the sampling clock φ₂.Therefore, by obtaining a further logical product of the logical productwhich is found by the AND gate 9 in light of Eq. 2 and activation of theburst gate pulse BGP, the phase reference signal ORG as that shown inFIG. 9 is obtained. In FIG. 9, the dotted line represents waveforms ofthe phase reference signal ORG as they would have been if activation ofthe burst gate pulse BGP was not a condition. In the example of FIG. 9,a sampling timing for creating the basic signal Y₅ serves as a base usedto detect the phase difference.

Returning to FIG. 2, the phase difference detecting circuit 5 will bedescribed. The phase difference detecting circuit 5 comprises inputterminals DIA_(<n:0>), DIB_(<n:0>) and DIC_(<n:0>) for respectivelyreceiving the three delayed basic signals DA_(<n:0>), DB_(<n:0>) andDC_(<n:0>) and output terminals L₁ and L₂ for respectively outputtingthe equivalent signal EQU and the non-equivalent signal UPDN.

The phase difference detecting circuit 5 judges whether the samplingclock is activated at a timing which is desirable for sampling. The"timing which is desirable for sampling" depends on a modulation methodof the color signal. The first preferred embodiment assumes that themodulation method is the NTSC method. The PAL method will be referred tolater in relation with other embodiments of the present invention.

FIG. 10 is a vector diagram showing a phase of the burst signal withrespect to the color-difference signals (R-Y) and (B-Y) in the NTSCmethod. In the NTSC method, since the vector of the burst signal is onthe axis (B-Y), sampling at the timing shown in FIG. 5, i.e., when θ=0°,90°, 180°, 270° , . . . is the most suitable. Hence, if the basicsignals sampled at different timings during a 180°-cycle have the samevalue, that fact is an evidence that the sampling was optimally timed.Otherwise, the sampling clock φ₂ leads or lags behind optimum timing.

FIG. 11 is a circuitry diagram showing an example of a structure of thephase difference detecting circuit 5. The phase difference detectingcircuit 5 comprises a magnitude comparator 7c and detects which one ofthe two delayed basic signals DA_(<n:0>) and DC_(<n:0>) has a largervalue in accordance with a predetermined rule. There is no need to dealwith the delayed basic signal DB_(<n:0>) in the NTSC method.

When sampling is optimally timed as evidenced by a fact that the twodelayed basic signals DA_(<n:0>) and DC_(<n:0>) have the same value, theequivalent signal EQU is activated to rise to "H" level. On the otherhand, when the delayed basic signal DA_(<n:0>) has a larger value thanthe delayed basic signal DC_(<n:0>), the non-equivalent signal UPDNrises to "H" level. This corresponds to where sampling is lagged behindoptimal timing as shown in FIGS. 6 and 7.

However, since the delayed basic signals are each serially updated asshown in FIG. 9 and the magnitude comparator 7c only compares theseupdated signals, even when the values S_(n+1) and S_(n+3) of the basicsignal shown in FIG. 8 are supplied respectively as the delayed basicsignals DA_(<n:0>) and DC_(<n:0>), the non-equivalent signal UPDN is at"H" level. In reality, FIG. 8 corresponds to where the timing ofsampling leads the optimal timing.

The phase reference signal ORG is used to eliminate this dichotomyregarding the non-equivalent signal UPDN. When the delayed basic signalDA_(<n:0>) has the value S_(n+1) of the basic signal, the phasereference signal ORG is not active. To the contrary, when the delayedbasic signal DA_(<n:0>) has the value S_(n) of the basic signal, thephase reference signal ORG is active.

The phase reference signal ORG is supplied to the sampling clockshifting circuit 2 together with the equivalent signal EQU and thenon-equivalent signal UPDN which form the phase difference signal sothat the phase difference signal serves as valid information which isuseful to judge whether the sampling timing leads or lags behind theoptimum timing.

When the sampling timing is leading the optimum timing, thenon-equivalent signal UPDN is at "L" level. Thus, due to the phasereference signal ORG, the dichotomy of the non-equivalent signal UPDN iseliminated.

Referring again to FIG. 2, the sampling clock shifting circuit 2 will bedescribed. The sampling clock shifting circuit 2 comprises inputterminals L₃ and L₄ for respectively receiving the equivalent signal EQUand the non-equivalent signal UPDN which form the phase differencesignal, an input terminal ENB for receiving the phase reference signalORG, the clock terminal CLK for receiving an original clock φ₁, and anoutput terminal L₅ for outputting the sampling clock φ₂.

The sampling clock shifting circuit 2 shifts the phase of the originalclock φ₁, whereby the sampling clock φ₂ is generated. This phaseshifting is performed in accordance with the phase difference signal andin light of the phase reference signal ORG.

For instance, the original clock φ₁ is obtained by multiplying thefrequency of a carrier which is synchronized with the chrominancesubcarrier four times by a resonance circuit which utilizes a PLLcircuit.

FIG. 12 is a circuitry diagram showing an example of a structure of thesampling clock shifting circuit 2. The sampling clock shifting circuit 2comprises delaying means 2a, a select signal generating circuit 2b,counter operation allowing means 2c, counting direction reversing means2d and shifting stopping means 2e.

The delaying means 2a includes a plurality of delaying elements 10₀, 10₁, . . . , 10_(n) which are serially connected to each other. Thedelaying element 10₀ receives the original clock φ₁, and the otherdelaying elements 10₁, 10₂ , . . . , 10_(n) receive outputs of previousdelaying elements 10₀, 10₁ , . . . , 10_(n-1), respectively. Outputs ofthe delaying elements 10₀, 10₁ , . . . , 10_(n) are supplied to ann-to-0 selector circuit 11. In accordance with data which is suppliedthrough a select terminal S_(<n:0>), the n-to-0 selector circuit 11selectively outputs at its output terminal Y either one of data receivedat its input terminals D₀, D₁ , . . . , D_(n). Since outputs of thedelaying elements 10₀, 10₁ , . . . , 10_(n) are supplied to the inputterminals D₀, D₁ , . . . , D_(n), respectively, it is possible for thedelaying means 2a to select and output a sampling clock out of clocksignals which are variously delayed, that is, which have differentphases from each other.

The select signal generating circuit 2b determines which data issupplied to the select terminal S_(<n:0>) when the phase differencesignal and the phase reference signal ORG are in which condition.

The select signal generating circuit 2b is formed by a counter 12. Thecounter 12 has an enable terminal E_(o), the clock terminal CLK, acarry-out terminal RCO, a count output terminal Q_(<n:0>) arid acounting direction control terminal UD.

When a signal supplied to the enable terminal E_(o) is at "H" level, thecounter 12 counts rises of a signal which is supplied to the clockterminal CLK. As to the direction of counting, the rises are counted upwhen a signal supplied to the counting direction control terminal UD isat "H" level, while the rises are counted down when a signal supplied tothe counting direction control terminal UD is at "L" level. A result ofthe counting is an (n+1)-bit signal which is outputted through the countoutput terminal Q_(<n:0>). The carry-out terminal RCO is activated likea pulse for every maximum count and a minimum count.

The counter operation allowing means 2c is connected to the enableterminal E_(o). The counter operation allowing means 2c includes aninverter 15a and an AND gate 13. If an output of the shifting stoppingmeans 2e should be disregarded, the level of a signal outputted by thecounter operation allowing means 2c would be "H" level when the phasereference signal ORG is at "H" level and the equivalent signal EQU is at"L" level.

In the counter operation allowing means 2c operating in such a manner,the equivalent signal EQU rises to "H" level when sampling is optimallytimed by the sampling clock φ₂, and therefore, the sampling clock φ₂ isnot shifted and the counter 12 does not operate. In addition, since thecounter 12 can operate only when the phase reference signal ORG is at"H" level, the dichotomy of the phase difference signal is eliminated.

The counting direction reversing means 2d includes an EXOR gate 14 andan RS flip-flop 16. As described later, in some cases, it is necessaryto advance the sampling clock although an advance of the sampling clockis detected by the phase difference signal. In such a case, the countingdirection reversing means 2d reverses the logic of the non-equivalentsignal UPDN and supplies the reversed logic to the counting directioncontrol terminal UD of the counter 12. Also in a case where it isnecessary to delay the sampling clock a delay of the sampling clock isdetected by the phase difference signal, the reversed logic of thenon-equivalent signal UPDN is supplied to the counting direction controlterminal UD.

The shifting stopping means 2e includes an (n+2)-bit OR gate 17, an(n+2)-bit NAND gate 18 and an inverter 15b. An output of the EXOR gate14 is supplied to an input terminal of the inverter 15b. An output ofthe counter 12 is supplied to an (n+1) bit of an input terminal of theOR gate 17, while an output of the inverter 15b is supplied to theremaining one bit of the input terminal of the OR gate 17. In a similarmanner, an output of the counter 12 is supplied to an (n+1) bit of theNAND gate 18 while an output of the inverter 15b is supplied to theremaining one bit of the NAND gate 18.

FIGS. 13 to 15 are timing charts showing waveforms of the respectivesignals. In the following, an operation of the shifting stopping means2e will be described while referring to the illustrated examples.

A) First Case (FIG. 13)

Where the sampling clock φ₂ is leading the optimum timing, to delay thesampling clock φ₂, the counter 12 counts in such a direction whichcauses its count to increment. At this point, a carry-out is notactivated yet, thereby allowing the non-equivalent signal UPDN to passthrough the EXOR gate 14 so that "L" level is available at the countingdirection control terminal UD (i.e., before a time t₁).

As the sampling clock φ₂ is shifted to lead the burst signal, thecounter 12 registers a maximum count (here, value "F" (=15)). When thecounter 12 registers a maximum count, every (n+1) bit of an output ofthe counter 12 is at the "H" level. These (n+1)-bit data are supplied tothe input terminal of the NAND gate 18.

When the carry-out is activated as a pulse, an output of the RSflip-flop 16 rises to "H" level to permit the EXOR gate 14 to functionas an inverter. Hence, even when the non-equivalent signal UPDN is stillat "L" level, the counter 12 receives "H" level at its countingdirection control terminal UD. This means that the counter 12 countsdown if it is allowed to continue counting.

The inverter 15b supplies "L" logic level to the rest portion of theinput terminal of the NAND gate 18, with a result that the NAND gate 18keeps outputting "H" logic level. This allows "H" level to keepappearing at the enable terminal E_(o) and hence the counting tocontinue. However, since the counter 12 counts down, the sampling clockφ₂ is shifted to lead the burst signal (i.e., after a time t₂).

Thus, there is a case where the phase of the sampling clock φ₂ isadvanced even though it is judged that the sampling clock φ₂ is alreadyleading the burst signal. Since the sampling clock φ₂ having a furtherdelay cannot be supplied any more, control performed here is aiming atfinding other clock signal. For example, assume that a phase difference(phase advance) of the sampling timing with respect to the optimaltiming is θ=-45° in terms of the phase of the burst signal. When anoutput of the delaying element 10_(n) is currently used as the samplingclock φ₂, by using a clock signal which has a further phase, advance of45° as the sampling clock φ₂ instead, it is possible to optimally timesampling. This is because sampling is performed for every quarter cycle(90°) of the burst signal.

In other words, since it is possible to know a phase advance and a phaselag in sampling during the period L (θ=-45°-45°), it has to be possibleto shift the sampling clock φ₂ in a range of at least one cycle of theoriginal clock θ₁.

When the sampling clock φ₂ advancing in this manner finally reaches theoptimum sampling timing, the equivalent signal EQU is activated. As aresult, the RS flip-flop 16 is reset and the EXOR gate 14 ceases toserve as an inverter (i.e., a time t₃).

Following this, counting up and counting down are repeated in accordancewith the logic of the non-equivalent signal UPDN, during which thesampling clock θ₂ automatically reaches the optimum sampling timing(i.e., after a time t₄).

B) Second Case (FIG. 14)

While the counter 12 registers a minimum count and the phase of thesampling clock φ₂ is further advanced in the first case, in the secondcase, the phase of the sampling clock φ₂ is delayed after a minimumcount is registered by the counter 12 and every (n+1) bit of an outputof the counter 12 falls to "L" level.

In FIG. 14, the waveforms are the same as they are in the first caseuntil the time t₁. However, after the counter 12 registers a minimumcount at the time t₁, it becomes necessary to delay the phase of thesampling clock φ₂ at the time t₂ ; that is, the non-equivalent signalUPDN rising to "H" level. Since "H" level is available from the RSflip-flop 16, the EXOR gate 14 reverses the non-equivalent signal UPDNto output "L" level. However, this "L" logic level is again reversed bythe inverter 15b and supplied to the input terminal of the NAND gate 18.

As a result, "H" level appears at every bit of the NAND gate 18 so that"L" level appears at the output terminal of the NAND gate 18. Hence, anoutput of the AND gate 13 is at "L" level and the counter 12 stopscounting.

The reason for disabling the counter 12 when it becomes necessary todelay the phase of the sampling clock φ₂ immediately after the counter12 has registered a minimum count is as follow.

First, since the counter 12 registered a minimum count at the time t₁,it was necessary to advance the phase of the sampling clock φ₂ up tothis point. On the other hand, it became necessary to delay the phase ofthe sampling clock φ₂ at the time t₂. Such a demand for the samplingclock φ₂ suggests that the current sampling clock is activated in thevicinity of the optimal sampling timing.

This situation could occur when a gap between the current sampling clockand the optimal sampling timing is smaller than a delay which is createdby each delaying element. In such a case, there is no need any more toshift the sampling clock φ₂. The counter 12 is stopped for this reason.

As it becomes necessary to advance the phase of the sampling clock φ₂ ata time t₅, counting down is started as in the first case.

C) Third Case (FIG. 15)

When the sampling clock φ₂ is behind the optimum sampling timing unlikein the first and the second cases, to advance the sampling clock φ₂, thecounter 12 starts counting in such a direction which causes its count todecrement. At this point, a carry-out is not activated yet, therebyallowing the non-equivalent signal UPDN to pass through the EXOR gate 14so that "H" level is available at the counting direction controlterminal UD (i.e., before a time t₆).

As the sampling clock φ₂ is shifted to be lagged behind the burstsignal, the counter 12 registers a minimum count "0." When the counter12 registers the minimum count, every (n+1) bit of an output of thecounter 12 falls to "L" level. These (n+1)-bit data are supplied to theinput terminal of the OR gate 17.

On the other hand, as in the second case, when the non-equivalent signalUPDN changes from "H" level to "L" level and it becomes accordinglynecessary to delay the sampling clock φ₂, the counter 12 is stopped.This is because every data supplied to the input terminal of the OR gate17 is "L" level (at a time t₇).

When it becomes necessary to advance the sampling clock φ₂, thenon-equivalent signal UPDN changes to "H" level However, since the EXORgate 14 reverses the non-equivalent signal UPDN and supplies the same tothe counting direction control terminal UD of the counter 12, thecounter 12 counts up and the phase of the sampling clock φ₂ is delayed.The reason for controlling in such a manner that the phase of thesampling clock φ₂ is delayed despite the need to advance the phase ofthe sampling clock φ₂ is the same as the reason described earlier foradvancing the phase of the sampling clock φ₂ despite the need to delaythe phase of the sampling clock φ₂.

Following this, the RS flip-flop 16 is resell as the equivalent signalEQU is activated. If the non-equivalent signal UPDN is at "H" level, thecounter 12 counts down to advance the sampling clock φ₂ (i.e., after atime t₉).

Briefly summarizing the operation in the first preferred embodiment, thephase difference detecting circuit 5 detects whether the sampling clockφ₂ has a phase advance or a phase lag with respect to the optimalsampling timing and outputs the phase difference signal. The phasereference signal ORG which is used as a reference to determine a phaseadvance and a phase lag is generated by the phase reference detectingcircuit 4. In accordance with these signals, the sampling clock shiftingcircuit 2 shifts the sampling clock φ₂ so that the sampling clock φ₂ isactivated at an optimal sampling timing. Sampling is performed inaccordance with such a sampling clock φ₂, whereby the basic signal isgenerated from which the phase reference signal ORG and the phasedifference signal (that is, the equivalent signal EQU and thenon-equivalent signal UPDN) are generated.

Thus, since a feedback regarding the sampling clock φ₂ is utilized, itis possible to automatically find an optimal sampling timing and controlthe phase of the sampling clock φ₂. Hence, during demodulation of thecolor signal, it is possible to avoid the conventional problems such asa distorted color phase.

C. Second Preferred Embodiment

A second preferred embodiment is a particularly preferable mode of thefirst preferred embodiment. As described with reference to FIGS. 13 to15, in some cases, the counter 12 registers a minimum count although thephase of the sampling clock φ₂ needs be advanced, while in some othercases, the counter 12 registers a maximum count despite a need fordelaying the phase of the sampling clock φ₂. In these cases, the phaseis delayed or advanced accordingly as described earlier in relation tothe first preferred embodiment, whereby the phase of the sampling clockφ₂ is adjusted to an optimal sampling timing.

Here, it is to be noted that the phase of the sampling clock φ₂ stayslargely deviated from the optimal sampling timing for a long time inmany such cases. The object of the second preferred embodiment is tomake such an undesirable situation less likely. That is, the secondpreferred embodiment is related to a technique for determining how muchthe delaying means 2a should delay the sampling clock φ₂, i.e., how muchdelays the delaying elements 10₀, 10₁ , . . . , 10_(n) should provide.

FIG. 16 is a timing chart showing waveforms of the original clock φ₁ andoutputs of the delaying elements 10₀, 10₁ , . . . , 10_(n). A delaycreated by each delaying element is set smaller than 1/2 cycle of theoriginal clock φ₁ (i.e., smaller than θ=45° in terms of the phase of theburst signal; 1/8 cycle). An output of the delaying element 10_(n) withthe largest delay arrives with a delay of 3/2 cycle of the originalclock φ₁ (that is, 3/8 cycle of the burst signal) from the originalclock φ₂. In other words, it is allowable to shift the sampling clock φ₂in the range of 3/2 cycle of the original clock φ₁.

If it was determined that the sampling clock φ₂ can be shifted in therange of only one cycle of the original clock φ₁, the following problemarises. In shifting the sampling clock φ₂ so that the sampling clock φ₂is activated at an optimal sampling timing, one of the cases in whichthe sampling clock φ₂ is shifted by the largest amount is where it isimpossible to delay the sampling clock φ₂ any more despite the samplingclock φ₂ having a little phase advance from the optimal sampling timing.In such a case, it is necessary to advance the phase by about 90° interms of the phase of the burst signal. That is, the counter 12 mustcount down from a maximum count to a minimum count on a count by countbasis. While the counter 12 counts down, any color signal inputtedduring this period cannot be sampled at a proper timing. Thus,"discontinuous sampling" is in progress during this period.

This problem is solved by further delaying the sampling clock φ₂. FIG.17 is a graph schematically illustrating shifting of the, sampling clockφ₂. A point P₁ is a sampling timing of the current sampling clock φ₂. Byshifting the point P₁ by about 90° to a point P₂, sampling is timedoptimally. On the other hand, by shifting the point P₁ toward a pointP₃, it is possible to smoothly and continuously perform sampling atoptimal timing (i.e., an a point P₀).

An allowable amount of a phase shift should be preferably set as amargin for both advancing and delaying the phase. The margin need not beset larger than 45° in terms of the phase of the burst signal sincesampling timing arises every 90°. Hence, allowable amounts for shiftingthe sampling clock φ₂ to solve the problem above is 90°+45°=135° as awhole, or 3/8 of the cycle of the burst signal is a necessary andsufficient amount.

D. Third Preferred Embodiment

FIG. 18 is a circuitry diagram showing a structure of a sampling circuit101 according to a third preferred embodiment of the present invention.The sampling circuit 101 is similar to the sampling circuit 100 of thefirst preferred embodiment as it is modified to replace the phasereference detecting circuit 4 with a phase reference detecting circuit41.

FIG. 19 is a circuitry diagram showing an example of a structure of thephase reference detecting circuit 41. The phase reference detectingcircuit 41 comprises (n+1)-bit D-type flip-flops 6a, 6b, 6c and 6d whichare serially connected to each other, (n+1)-bit magnitude comparators 7aand 7b, an OR gate 8 and an AND gate 9. The D-type flip-flops 6a, 6b, 6cand 6d output delayed basic signals DD_(<n:0>), DC_(<n:0>), DB_(<n:0>)and DA_(<n:0>), respectively, which are obtained by delaying the basicsignal D_(<n:0>) at activation of the sampling clock φ₂.

In the circuit of FIG. 19, the D-type flip-flops 6a, 6b and 6c operatein a similar manner to the D-type flip-flops 6b, 6c and 6d of thecircuit of FIG. 4. Hence, the phase reference signal ORG is activatedwhile the delayed basic signal DB_(<n:0>) is within the range ofθ=-45°-45°.

FIG. 20 is a circuitry diagram showing another example of a structure ofthe phase reference detecting circuit 41. In the circuit of FIG. 20, theD-type flip-flops 6b, 6c and 6d operate in a similar manner to theD-type flip-flops 6b, 6c and 6d of the circuit of FIG. 4. Hence, thephase reference signal ORG is activated while the delayed basic signalDA_(<n:0>) is within the range of θ=-45°-45°. It then follows that arelation between the phase reference signal ORG, the basic signalD_(<n:0>) and the delayed basic signals DD_(<n:0>), DC_(<n:0>),DB_(<n:0>) and DA_(<n:0>) is as shown in the timing chart of FIG. 21.

FIG. 22 is a circuitry diagram showing still another example of astructure of the phase reference detecting circuit 41. From FIGS. 5 to8, it is understood that the timing at which the basic signal has thevalue S_(n) is within the range of θ=-45°-45° if Eq. 4 is satisfied.

    S.sub.n+2 ≧S.sub.n+3 and S.sub.n+3 <S.sub.n         (Eq. 4)

Judgement performed by the magnitude comparator 7a and the OR gate 8 isin light of the first condition of Eq. 4, and judgement performed by themagnitude comparator 7b is in light of the second condition of Eq. 4. Bycreating a logical product of the two judgement results by the AND gate9, a comprehensive judgement in light of Eq. 4 as a whole is yielded.

In the circuit of FIG. 22, the phase reference signal ORG is activatedwhile the delayed basic signal DA_(<n:0>) is within the range ofθ=-45°-45°.

FIG. 23 is a circuitry diagram showing a further example of a structureof the phase reference detecting circuit 41. From FIGS. 5 to 8, it isunderstood that the timing at which the basic signal has the value S_(n)is within the range of θ=-45°- 45° if Eq. 5 is satisfied.

    S.sub.n ≦S.sub.n+1 and S.sub.n+3 <S.sub.n           (Eq. 5)

Judgement performed by the magnitude comparator 7a and the OR gate 8 isin light of the first condition of Eq. 5, and judgement performed by themagnitude comparator 7b is in light of the second condition of Eq. 5. Bycreating a logical product of the two judgement results by the AND gate9, a comprehensive judgement in light of Eq. 5 as a whole is yielded.

In the circuit of FIG. 23, the phase reference signal ORG is activatedwhile the delayed basic signal DA_(<n:0>) is within the range ofθ=-45°-45°.

Thus, these four types of the delayed basic signals may be generated toobtain the phase reference signal ORG from the three of the four typesof the delayed basic signals.

E. Fourth Preferred Embodiment

FIG. 24 is a circuitry diagram showing a structure of the phasedifference detecting circuit 5 according to a fourth preferredembodiment of the present invention. The phase difference detectingcircuit 5 comprises magnitude comparators 7d and 7e. According to apredetermined rule, the phase difference detecting circuit 5 detectswhich one of the three delayed basic signals DA_(<n:0>), DB_(<n:0>) andDC_(<n:0>) is larger than the other two.

FIG. 25 is a vector diagram showing the phase of the burst signal withrespect to the color-difference signals (R-Y) and (B-Y) in the PALmethod. In the PAL method, since the vector of the burst signal hasphase differences of +135° and -135° with respect to the axis (B-Y),sampling at the timing shown in FIG. 7, i.e., when θ=45°, 135°, 225°,315°, . . . is the most suitable.

Hence, when values of the basic signal sampled at a consecutive timingare equal to each other, the equivalent signal EQU is at "H" level. Themagnitude comparator 7d is used to realize this.

On the other hand, since the situation of FIG. 5 is evoked when twovalues of the basic signal sampled at every other timing are equal toeach other, it is judged that the phase is lagged behind by 45°. Ofthese two values of the basic signal, if the value resulted by the earlysampling is larger than the other, the situation corresponds to FIG. 6where it is judged that there is a phase lag and the non-equivalentsignal UPDN rises to "H" level. The purpose of providing the magnitudecomparator 7e and an OR gate 9a is to realize this.

Thus, according to the fourth preferred embodiment, as in the NTSCmethod described earlier in relation to the first preferred embodiment,it is possible to automatically find an optimal sampling timing andcontrol the phase of the sampling clock φ₂ in the PAL method as well.

While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

We claim:
 1. A sampling circuit for sampling an analogsignal-to-be-sampled using a sampling clock, said signal-to-be-sampledincluding a primary signal which is obtained by demodulating a carriersignal, and a fore signal which has a same frequency as said carriersignal and which is precedent to said primary signal, said samplingclock having a frequency which is m times as high as the frequency ofsaid carrier signal (m is an integer), said sampling circuitcomprising:(a) an A/D converter for sampling said signal-to-be-sampledin accordance with said sampling clock and generating a digital basicsignal; (b) a phase reference detecting circuit for receiving thedigital basic signal from the A/D converter and for generating at leastthree delayed basic signals having different phases from each other andbeing obtained by delaying said basic signal in synchronism with saidsampling clock, and a phase reference signal which indicates a referenceof a phase of said sampling clock; (c) a phase difference detectingcircuit for receiving the delayed signals from the phase referencedetecting circuit and for generating a phase difference signal from saiddelayed basic signals, said phase difference signal indicating a phasedifference between said fore signal and said basic signal when saidphase reference signal is active; and (d) a sampling clock shiftingcircuit for receiving the phase difference signal from the phasedifference detecting circuit and the phase reference signal from thephase reference detecting circuit and for shifting the phase of saidsampling clock in accordance with said phase difference signal only whensaid phase reference signal is active, to thereby supply said samplingclock to said converter and said phase reference detecting circuit. 2.The sampling circuit of claim 1, wherein said phase reference signal isactivated during a specified one cycle of said sampling clock whichstarts from a time of activation of said sampling clock within a rangeof 1/2m cycle from a mid value of said fore signal toward both a priortime and a future time.
 3. The sampling circuit of claim 2, wherein saidinteger m is 4,and wherein said phase reference detecting circuitincludes: (b-1) first signal transmitting means having an input terminalfor receiving said basic signal and an output terminal for transmittinga signal which is received at said input terminal in response toactivation of said sampling clock as a first delayed basic signal ofsaid delayed basic signals; (b-2) second signal transmitting meanshaving an input terminal for receiving said first delayed basic signaland an output terminal for transmitting a signal which is supplied tosaid input terminal of said second signal transmitting means in responseto activation of said sampling clock as a second delayed basic signal ofsaid delayed basic signals; (b-3) third signal transmitting means havingan input terminal for receiving said second delayed basic signal and anoutput terminal for transmitting a signal which is supplied to saidinput terminal of said third signal transmitting means in response toactivation of said sampling clock as a third delayed basic signal ofsaid delayed basic signals; (b-4) fourth signal transmitting meanshaving an input terminal for receiving said third delayed basic signaland an output terminal for transmitting a signal which is supplied tosaid input terminal of said fourth signal transmitting means in responseto activation of said sampling clock as a fourth delayed basic signal ofsaid delayed basic signals; and (b-5) a comparator for outputting saidphase reference signal which is activated when said first delayed basicsignal is smaller in delay than said fourth delayed basic signal and isequal to or smaller in delay than said second delayed basic signalduring said specified one cycle of said fore signal.
 4. The samplingcircuit of claim 2, wherein said integer m is 4, andwherein said phasereference detecting circuit includes: (b-1) first signal transmittingmeans having an input terminal for receiving said basic signal and anoutput terminal for transmitting a signal which is received at saidinput terminal in response to activation of said sampling clock as afirst delayed basic signal of said delayed basic signals; (b-2) secondsignal transmitting means having an input terminal for receiving saidfirst delayed basic signal and an output terminal for transmitting asignal which is supplied to said input terminal of said second signaltransmitting means in response to activation of said sampling clock as asecond delayed basic signal of said delayed basic signals; (b-3) thirdsignal transmitting means having an input terminal for receiving seconddelayed basic signal and an output terminal for transmitting a signalwhich is supplied to said input terminal of said third signaltransmitting means in response to activation of said sampling clock as athird delayed basic signal of said delayed basic signals; (b-4) fourthsignal transmitting means having an input terminal for receiving saidthird delayed basic signal and an output terminal for transmitting asignal which is supplied to said input terminal of said fourth signaltransmitting means in response to activation of said sampling clock as afourth delayed basic signal of said delayed basic signals; and (b-5) acomparator for outputting said phase reference signal which is activatedwhen said fourth delayed basic signal is larger in delay than said firstdelayed basic signal and is equal to or smaller in delay than said thirddelayed basic signal during said specified one cycle of said foresignal.
 5. The sampling circuit of claim 2, wherein said integer m is4,and wherein said phase reference detecting circuit includes: (b-1)first signal transmitting means having an input terminal for receivingsaid basic signal and an output terminal for transmitting a signal whichis received at said input terminal in response to activation of saidsampling clock as a first delayed basic signal of said delayed basicsignals; (b-2) second signal transmitting means having an input terminalfor receiving said first delayed basic signal and an output terminal fortransmitting a signal which is supplied to said input terminal of saidsecond signal transmitting means in response to activation of saidsampling clock as a second delayed basic signal of said delayed basicsignals; (b-3) third signal transmitting means having an input terminalfor receiving said second delayed basic signal and an output terminalfor transmitting a signal which is supplied to said input terminal ofsaid third signal transmitting means in response to activation of saidsampling clock as a third delayed basic signal of said delayed basicsignals; and (b-4) a first comparator for outputting said phasereference signal which is activated when said second delayed basicsignal is larger in delay than said first delayed basic signal and saidthird delayed basic signal is equal to or smaller in delay than saidsecond delayed basic signal during said specified one cycle of said foresignal.
 6. The sampling circuit of claim 5, wherein said phasedifference detecting circuit includes (c-1) a second comparator forcomparing said third and said first delayed basic signals and foroutputting an equivalent signal which is activated when said third andsaid first delayed basic signals are equal in delay to each other and anon-equivalent signal which is activated when said third delayed basicsignal is larger in delay than said first delayed basic signal,andwherein said equivalent signal and said non-equivalent signal form saidphase difference signal.
 7. The sampling circuit of claim 5, whereinsaid phase difference detecting circuit includes:(c-1) a secondcomparator for outputting an equivalent signal which is activated whensaid third and said second delayed basic signals are in delay equal toeach other; and (c-2) a third comparator for outputting a non-equivalentsignal which is activated when said third delayed basic signal is equalin delay to or larger than said first delayed basic signal, and whereinsaid equivalent signal and said non-equivalent signal form said phasedifference signal.
 8. The sampling circuit of claim 2, wherein saidphase difference signal is formed by an equivalent signal which isactivated when said. signal-to-be-sampled is sampled at an optimaltiming and a non-equivalent signal which indicates, during activation ofsaid phase reference signal, that the activation expresses a timingdelay of sampling,and wherein said sampling clock shifting circuitincludes: (d-1) delaying means for receiving a shifting control signaland said sampling clock and delaying said sampling clock in accordancewith said shifting control signal; (d-2) a counter for counting saidsampling clock which is delayed by said delaying means and generatingsaid shifting control signal, a direction in which said counter countsbeing determined by said non-equivalent signal; and (d-3) counteroperation allowing means for allowing said counter to count only whensaid non-equivalent signal is not active but said phase reference signalis active.
 9. The sampling circuit of claim 8, wherein said delayingmeans includes:(d-1-1) a plurality of delaying elements which areserially connected to each other; (d-1-2) the same number of inputterminals as said plurality of said delaying elements, each receiving anoutput of an associated one of said delaying elements; and (d-1-3) aselector for selectively outputting one of data supplied to said inputterminals in accordance with said shifting control signal.
 10. Thesampling circuit of claim 8, wherein said counter includes (d-2-1) anenable terminal for controlling an operation of said counter,and whereinsaid counter operation allowing means includes: (d-3-1) an inverter forreversing said equivalent signal; and (d-3-2) a logic element having aninput terminal for receiving an output of said inverter and said phasereference signal and an output terminal for outputting a logical productwhich is obtained at said input terminal of said logic element, said,output terminal of said logic element being connected to said enableterminal.
 11. The sampling circuit of claim 8, wherein said samplingclock shifting circuit further includes (d-4) counting directionreversing means for reversing a counting direction when said counterregisters a maximum count or a minimum count.
 12. The sampling circuitof claim 11, wherein said counter outputs a carry-out signal which isactivated when said counter registers said maximum count or said minimumcount,and wherein said counting direction reversing means includes:(d-4-1) a flip-flop for outputting a reversing control signal which isset by said carry-out signal and reset by said equivalent signal; and(d-4-2) a logic element for transmitting said non-equivalent signal inresponse to deactivation of said reversing control signal and forreversing and transmitting said non-equivalent signal in response toactivation of said reversing control signal.
 13. The sampling circuit ofclaim 11, wherein said delaying means shifts said sampling clock withina range of 3/8 cycle of said fore signal.
 14. The sampling circuit ofclaim 11, wherein said sampling clock shifting circuit further includes(d-5) counting stopping means for prohibiting counting up when saidcounter registers said maximum count and prohibiting counting down whensaid counter registers said minimum count.
 15. A phase referencedetecting circuit for generating a basic signal by sampling asignal-to-be-sampled in accordance with a sampling clock which isactivated at intervals of a specified 1/4 cycle of saidsignal-to-be-sampled and for outputting a phase reference signal whichserves as a reference to determine whether said signal-to-be-sampled issampled with a predetermined phase and which is activated in response tosaid basic signal, said phase reference detecting circuit comprising:(a)first signal transmitting means having an input terminal for receivingsaid basic signal and an output terminal for transmitting a signal whichis received at said input terminal in response to activation of saidsampling clock, said signal from said output terminal being outputted asa first delayed basic signal; (b) second signal transmitting meanshaving an input terminal for receiving said first delayed basic signaland an output terminal for transmitting a signal which is supplied tosaid input terminal of said second signal transmitting means in responseto activation of said sampling clock, said signal from said outputterminal being outputted as a second delayed basic signal; (c) thirdsignal transmitting means having an input terminal for receiving saidsecond delayed basic signal and an output terminal for transmitting asignal which is supplied to said input terminal of said third signaltransmitting means in response to activation of said sampling clock,said signal from said output terminal being outputted as a third delayedbasic signal; and (d) a first comparator for receiving the first,second, and third delayed basic signals and for outputting said phasereference signal which is activated when said second delayed basicsignal is larger in delay than said first delayed basic signal and saidthird delayed basic signal is equal to or smaller in delay than saidsecond delayed basic signal during said specified cycle of said foresignal.
 16. A sampling clock shifting circuit for shifting a phase of asampling clock during sampling of a signal-to-be-sampled in accordancewith said sampling clock which is activated at intervals of 1/4 cycle ofsaid signal-to-be-sampled in such a manner that saidsignal-to-be-sampled is sampled with a predetermined phase, saidsampling clock shifting circuit receiving:(x-1) a coincidence signalwhich indicates whether a phase of said sampling clock is deviated fromsaid predetermined phase; (x-2) a phase reference signal which expressesa deviation between the phase of said sampling clock and saidpredetermined phase; and (x-3) a non-coincidence signal which expressesa direction of the deviation between the phase of said sampling clockand said predetermined phase when said phase reference signal is active,said sampling clock shifting circuit comprising: (a) delaying means forreceiving a shifting control signal and said sampling clock and delayingsaid sampling clock in accordance with said shifting control signal; (b)a counter for counting said sampling clock which is delayed by saiddelaying means and generating said shifting control signal, a directionin which said counter counts being determined by said non-coincidencesignal; and (c) counter operation allowing means for allowing saidcounter to count only when said coincident signal is not active but saidphase reference signal is active.